Altium

Design Rule Verification Report

Date: 2021-04-12
Time: 11:50:53 PM
Elapsed Time: 00:00:02
Filename: C:\SunseekerTelemetry\Hardware\AltiumProject\2020-2021 Telemetry Board\Stage 2 - Combined.PcbDoc
Warnings: 2
Rule Violations: 107

Summary

Warnings Count
Zero hole size multi-layer pad(s) detected 1
Multilayer Pads with 0 size Hole found 1
Total 2

Rule Violations Count
Clearance Constraint (Gap=0.2mm) (OnLayer('Bottom Layer')),(All) 0
Clearance Constraint (Gap=0.2mm) (OnLayer('Top Layer')),(All) 0
Clearance Constraint (Gap=0.2mm) (All),(All) 0
Short-Circuit Constraint (Allowed=No) (All),(All) 0
Un-Routed Net Constraint ( (All) ) 0
Modified Polygon (Allow modified: No), (Allow shelved: No) 0
Width Constraint (Min=0.127mm) (Max=2.54mm) (Preferred=0.254mm) (All) 0
Width Constraint (Min=0.09mm) (Max=2.54mm) (Preferred=0.254mm) (OnLayer('Top Layer')) 0
Width Constraint (Min=0.09mm) (Max=2.54mm) (Preferred=0.254mm) (OnLayer('Bottom Layer')) 0
Power Plane Connect Rule(Relief Connect )(Expansion=0.508mm) (Conductor Width=0.254mm) (Air Gap=0.254mm) (Entries=4) (All) 0
Minimum Annular Ring (Minimum=0.13mm) (All) 12
Hole Size Constraint (Min=0.2mm) (Max=6.3mm) (All) 0
Hole To Hole Clearance (Gap=0.254mm) (All),(All) 0
Minimum Solder Mask Sliver (Gap=0.1mm) (All),(All) 28
Silk To Solder Mask (Clearance=0.15mm) (IsPad),(All) 59
Silk to Silk (Clearance=0mm) (All),(All) 0
Net Antennae (Tolerance=0mm) (All) 8
Room CANbus_0 (Bounding Region = (893.5mm, 470mm, 973.5mm, 492.5mm) (InComponentClass('CANbus_0')) 0
Room ESP32_0 (Bounding Region = (1111.5mm, 440.5mm, 1178.5mm, 474.5mm) (InComponentClass('ESP32_0')) 0
Room MCU JTAG_0 (Bounding Region = (1016.5mm, 480mm, 1043mm, 492.5mm) (InComponentClass('MCU JTAG_0')) 0
Room CANbus_1 (Bounding Region = (893.5mm, 427.5mm, 973.5mm, 450mm) (InComponentClass('CANbus_1')) 0
Room RTC_0 (Bounding Region = (1021.5mm, 356.5mm, 1057.5mm, 405.5mm) (InComponentClass('RTC_0')) 0
Room RS-232_0 (Bounding Region = (1130mm, 402.5mm, 1182mm, 436.5mm) (InComponentClass('RS-232_0')) 0
Room GPS_0 (Bounding Region = (877.5mm, 365mm, 958mm, 420.5mm) (InComponentClass('GPS_0')) 0
Room Main (Bounding Region = (1000.5mm, 423.5mm, 1065mm, 476.5mm) (InComponentClass('Main')) 0
Room IMU_0 (Bounding Region = (1067.5mm, 350.5mm, 1093.5mm, 393mm) (InComponentClass('IMU_0')) 0
Room SMPS_DOWN (Bounding Region = (940mm, 496mm, 1011.5mm, 523mm) (InComponentClass('SMPS_DOWN')) 0
Room UART_ESP32 (Bounding Region = (1095mm, 480.5mm, 1179.5mm, 509.5mm) (InComponentClass('UART_ESP32')) 0
Room SD Card_0 (Bounding Region = (967.5mm, 349.5mm, 1014.5mm, 393.5mm) (InComponentClass('SD Card_0')) 0
Room Supercapacitor0 (Bounding Region = (989.5mm, 444.5mm, 1030.5mm, 479.5mm) (InComponentClass('Supercapacitor0')) 0
Room MCU Reset Button_0 (Bounding Region = (899mm, 508.5mm, 922mm, 521mm) (InComponentClass('MCU Reset Button_0')) 0
Room MCU USB-UART_0 (Bounding Region = (1103mm, 370.5mm, 1179.5mm, 399mm) (InComponentClass('MCU USB-UART_0')) 0
Room MCU Power_0 (Bounding Region = (1013mm, 408mm, 1062mm, 457mm) (InComponentClass('MCU Power_0')) 0
Room MCU LEDs_0 (Bounding Region = (1067mm, 418mm, 1085.5mm, 451.5mm) (InComponentClass('MCU LEDs_0')) 0
Room MCU Button_0 (Bounding Region = (1155.5mm, 355mm, 1179.5mm, 367mm) (InComponentClass('MCU Button_0')) 0
Height Constraint (Min=0mm) (Max=25.4mm) (Prefered=12.7mm) (All) 0
Total 107

Warnings

Zero hole size multi-layer pad(s) detected
Pad U8-38(249.7mm,109.25mm) on Multi-Layer on Net GND
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Multilayer Pads with 0 size Hole found
Pad U8-38(249.7mm,109.25mm) on Multi-Layer
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Minimum Annular Ring (Minimum=0.13mm) (All)
Minimum Annular Ring: (Collision < 0.13mm) Via (248.3mm,108.55mm) from Top Layer to Bottom Layer (Annular Ring=0mm) On (Top Layer)
Minimum Annular Ring: (Collision < 0.13mm) Via (248.3mm,109.95mm) from Top Layer to Bottom Layer (Annular Ring=0mm) On (Top Layer)
Minimum Annular Ring: (Collision < 0.13mm) Via (249.7mm,108.55mm) from Top Layer to Bottom Layer (Annular Ring=0mm) On (Top Layer)
Minimum Annular Ring: (Collision < 0.13mm) Via (249.7mm,109.95mm) from Top Layer to Bottom Layer (Annular Ring=0mm) On (Top Layer)
Minimum Annular Ring: (Collision < 0.13mm) Via (249mm,107.85mm) from Top Layer to Bottom Layer (Annular Ring=0mm) On (Top Layer)
Minimum Annular Ring: (Collision < 0.13mm) Via (249mm,109.25mm) from Top Layer to Bottom Layer (Annular Ring=0mm) On (Top Layer)
Minimum Annular Ring: (Collision < 0.13mm) Via (249mm,110.65mm) from Top Layer to Bottom Layer (Annular Ring=0mm) On (Top Layer)
Minimum Annular Ring: (Collision < 0.13mm) Via (250.4mm,107.85mm) from Top Layer to Bottom Layer (Annular Ring=0mm) On (Top Layer)
Minimum Annular Ring: (Collision < 0.13mm) Via (250.4mm,109.25mm) from Top Layer to Bottom Layer (Annular Ring=0mm) On (Top Layer)
Minimum Annular Ring: (Collision < 0.13mm) Via (250.4mm,110.65mm) from Top Layer to Bottom Layer (Annular Ring=0mm) On (Top Layer)
Minimum Annular Ring: (Collision < 0.13mm) Via (251.1mm,108.55mm) from Top Layer to Bottom Layer (Annular Ring=0mm) On (Top Layer)
Minimum Annular Ring: (Collision < 0.13mm) Via (251.1mm,109.95mm) from Top Layer to Bottom Layer (Annular Ring=0mm) On (Top Layer)
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Minimum Solder Mask Sliver (Gap=0.1mm) (All),(All)
Minimum Solder Mask Sliver Constraint: (0.054mm < 0.1mm) Between Pad U9_1-1(228mm,148.5mm) on Top Layer And Pad U9_1-2(228mm,147.865mm) on Top Layer [Top Solder] Mask Sliver [0.054mm]
Minimum Solder Mask Sliver Constraint: (0.054mm < 0.1mm) Between Pad U9_1-10(233.334mm,144.69mm) on Top Layer And Pad U9_1-11(233.334mm,145.325mm) on Top Layer [Top Solder] Mask Sliver [0.054mm]
Minimum Solder Mask Sliver Constraint: (0.054mm < 0.1mm) Between Pad U9_1-10(233.334mm,144.69mm) on Top Layer And Pad U9_1-9(233.334mm,144.055mm) on Top Layer [Top Solder] Mask Sliver [0.054mm]
Minimum Solder Mask Sliver Constraint: (0.054mm < 0.1mm) Between Pad U9_1-11(233.334mm,145.325mm) on Top Layer And Pad U9_1-12(233.334mm,145.96mm) on Top Layer [Top Solder] Mask Sliver [0.054mm]
Minimum Solder Mask Sliver Constraint: (0.054mm < 0.1mm) Between Pad U9_1-12(233.334mm,145.96mm) on Top Layer And Pad U9_1-13(233.334mm,146.595mm) on Top Layer [Top Solder] Mask Sliver [0.054mm]
Minimum Solder Mask Sliver Constraint: (0.054mm < 0.1mm) Between Pad U9_1-13(233.334mm,146.595mm) on Top Layer And Pad U9_1-14(233.334mm,147.23mm) on Top Layer [Top Solder] Mask Sliver [0.054mm]
Minimum Solder Mask Sliver Constraint: (0.054mm < 0.1mm) Between Pad U9_1-14(233.334mm,147.23mm) on Top Layer And Pad U9_1-15(233.334mm,147.865mm) on Top Layer [Top Solder] Mask Sliver [0.054mm]
Minimum Solder Mask Sliver Constraint: (0.054mm < 0.1mm) Between Pad U9_1-15(233.334mm,147.865mm) on Top Layer And Pad U9_1-16(233.334mm,148.5mm) on Top Layer [Top Solder] Mask Sliver [0.054mm]
Minimum Solder Mask Sliver Constraint: (0.054mm < 0.1mm) Between Pad U9_1-2(228mm,147.865mm) on Top Layer And Pad U9_1-3(228mm,147.23mm) on Top Layer [Top Solder] Mask Sliver [0.054mm]
Minimum Solder Mask Sliver Constraint: (0.054mm < 0.1mm) Between Pad U9_1-3(228mm,147.23mm) on Top Layer And Pad U9_1-4(228mm,146.595mm) on Top Layer [Top Solder] Mask Sliver [0.054mm]
Minimum Solder Mask Sliver Constraint: (0.054mm < 0.1mm) Between Pad U9_1-4(228mm,146.595mm) on Top Layer And Pad U9_1-5(228mm,145.96mm) on Top Layer [Top Solder] Mask Sliver [0.054mm]
Minimum Solder Mask Sliver Constraint: (0.054mm < 0.1mm) Between Pad U9_1-5(228mm,145.96mm) on Top Layer And Pad U9_1-6(228mm,145.325mm) on Top Layer [Top Solder] Mask Sliver [0.054mm]
Minimum Solder Mask Sliver Constraint: (0.054mm < 0.1mm) Between Pad U9_1-6(228mm,145.325mm) on Top Layer And Pad U9_1-7(228mm,144.69mm) on Top Layer [Top Solder] Mask Sliver [0.054mm]
Minimum Solder Mask Sliver Constraint: (0.054mm < 0.1mm) Between Pad U9_1-7(228mm,144.69mm) on Top Layer And Pad U9_1-8(228mm,144.055mm) on Top Layer [Top Solder] Mask Sliver [0.054mm]
Minimum Solder Mask Sliver Constraint: (0.054mm < 0.1mm) Between Pad U9_2-1(229mm,38.5mm) on Top Layer And Pad U9_2-2(229mm,37.865mm) on Top Layer [Top Solder] Mask Sliver [0.054mm]
Minimum Solder Mask Sliver Constraint: (0.054mm < 0.1mm) Between Pad U9_2-10(234.334mm,34.69mm) on Top Layer And Pad U9_2-11(234.334mm,35.325mm) on Top Layer [Top Solder] Mask Sliver [0.054mm]
Minimum Solder Mask Sliver Constraint: (0.054mm < 0.1mm) Between Pad U9_2-10(234.334mm,34.69mm) on Top Layer And Pad U9_2-9(234.334mm,34.055mm) on Top Layer [Top Solder] Mask Sliver [0.054mm]
Minimum Solder Mask Sliver Constraint: (0.054mm < 0.1mm) Between Pad U9_2-11(234.334mm,35.325mm) on Top Layer And Pad U9_2-12(234.334mm,35.96mm) on Top Layer [Top Solder] Mask Sliver [0.054mm]
Minimum Solder Mask Sliver Constraint: (0.054mm < 0.1mm) Between Pad U9_2-12(234.334mm,35.96mm) on Top Layer And Pad U9_2-13(234.334mm,36.595mm) on Top Layer [Top Solder] Mask Sliver [0.054mm]
Minimum Solder Mask Sliver Constraint: (0.054mm < 0.1mm) Between Pad U9_2-13(234.334mm,36.595mm) on Top Layer And Pad U9_2-14(234.334mm,37.23mm) on Top Layer [Top Solder] Mask Sliver [0.054mm]
Minimum Solder Mask Sliver Constraint: (0.054mm < 0.1mm) Between Pad U9_2-14(234.334mm,37.23mm) on Top Layer And Pad U9_2-15(234.334mm,37.865mm) on Top Layer [Top Solder] Mask Sliver [0.054mm]
Minimum Solder Mask Sliver Constraint: (0.054mm < 0.1mm) Between Pad U9_2-15(234.334mm,37.865mm) on Top Layer And Pad U9_2-16(234.334mm,38.5mm) on Top Layer [Top Solder] Mask Sliver [0.054mm]
Minimum Solder Mask Sliver Constraint: (0.054mm < 0.1mm) Between Pad U9_2-2(229mm,37.865mm) on Top Layer And Pad U9_2-3(229mm,37.23mm) on Top Layer [Top Solder] Mask Sliver [0.054mm]
Minimum Solder Mask Sliver Constraint: (0.054mm < 0.1mm) Between Pad U9_2-3(229mm,37.23mm) on Top Layer And Pad U9_2-4(229mm,36.595mm) on Top Layer [Top Solder] Mask Sliver [0.054mm]
Minimum Solder Mask Sliver Constraint: (0.054mm < 0.1mm) Between Pad U9_2-4(229mm,36.595mm) on Top Layer And Pad U9_2-5(229mm,35.96mm) on Top Layer [Top Solder] Mask Sliver [0.054mm]
Minimum Solder Mask Sliver Constraint: (0.054mm < 0.1mm) Between Pad U9_2-5(229mm,35.96mm) on Top Layer And Pad U9_2-6(229mm,35.325mm) on Top Layer [Top Solder] Mask Sliver [0.054mm]
Minimum Solder Mask Sliver Constraint: (0.054mm < 0.1mm) Between Pad U9_2-6(229mm,35.325mm) on Top Layer And Pad U9_2-7(229mm,34.69mm) on Top Layer [Top Solder] Mask Sliver [0.054mm]
Minimum Solder Mask Sliver Constraint: (0.054mm < 0.1mm) Between Pad U9_2-7(229mm,34.69mm) on Top Layer And Pad U9_2-8(229mm,34.055mm) on Top Layer [Top Solder] Mask Sliver [0.054mm]
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Silk To Solder Mask (Clearance=0.15mm) (IsPad),(All)
Silk To Solder Mask Clearance Constraint: (Collision < 0.15mm) Between Pad J3_1-5(17.54mm,135.77mm) on Multi-Layer And Track (18.048mm,125.737mm)(18.048mm,145.803mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0mm]
Silk To Solder Mask Clearance Constraint: (Collision < 0.15mm) Between Pad J3_2-5(17.54mm,93.27mm) on Multi-Layer And Track (18.048mm,83.237mm)(18.048mm,103.303mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0mm]
Silk To Solder Mask Clearance Constraint: (0.131mm < 0.15mm) Between Pad L2-2(57.86mm,152.913mm) on Top Layer And Track (37.508mm,151.008mm)(104.12mm,151.008mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.131mm]
Silk To Solder Mask Clearance Constraint: (0.124mm < 0.15mm) Between Pad LED1-1(178mm,75.5mm) on Top Layer And Track (173.936mm,73.976mm)(179.016mm,73.976mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.124mm]
Silk To Solder Mask Clearance Constraint: (0.124mm < 0.15mm) Between Pad LED1-1(178mm,75.5mm) on Top Layer And Track (173.936mm,77.024mm)(179.016mm,77.024mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.124mm]
Silk To Solder Mask Clearance Constraint: (0.124mm < 0.15mm) Between Pad LED1-2(175mm,75.5mm) on Top Layer And Track (173.936mm,73.976mm)(179.016mm,73.976mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.124mm]
Silk To Solder Mask Clearance Constraint: (0.124mm < 0.15mm) Between Pad LED1-2(175mm,75.5mm) on Top Layer And Track (173.936mm,77.024mm)(179.016mm,77.024mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.124mm]
Silk To Solder Mask Clearance Constraint: (0.124mm < 0.15mm) Between Pad LED2-1(178mm,83.5mm) on Top Layer And Track (173.936mm,81.976mm)(179.016mm,81.976mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.124mm]
Silk To Solder Mask Clearance Constraint: (0.124mm < 0.15mm) Between Pad LED2-1(178mm,83.5mm) on Top Layer And Track (173.936mm,85.024mm)(179.016mm,85.024mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.124mm]
Silk To Solder Mask Clearance Constraint: (0.124mm < 0.15mm) Between Pad LED2-2(175mm,83.5mm) on Top Layer And Track (173.936mm,81.976mm)(179.016mm,81.976mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.124mm]
Silk To Solder Mask Clearance Constraint: (0.124mm < 0.15mm) Between Pad LED2-2(175mm,83.5mm) on Top Layer And Track (173.936mm,85.024mm)(179.016mm,85.024mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.124mm]
Silk To Solder Mask Clearance Constraint: (0.124mm < 0.15mm) Between Pad LED3-1(178mm,91.5mm) on Top Layer And Track (173.936mm,89.976mm)(179.016mm,89.976mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.124mm]
Silk To Solder Mask Clearance Constraint: (0.124mm < 0.15mm) Between Pad LED3-1(178mm,91.5mm) on Top Layer And Track (173.936mm,93.024mm)(179.016mm,93.024mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.124mm]
Silk To Solder Mask Clearance Constraint: (0.124mm < 0.15mm) Between Pad LED3-2(175mm,91.5mm) on Top Layer And Track (173.936mm,89.976mm)(179.016mm,89.976mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.124mm]
Silk To Solder Mask Clearance Constraint: (0.124mm < 0.15mm) Between Pad LED3-2(175mm,91.5mm) on Top Layer And Track (173.936mm,93.024mm)(179.016mm,93.024mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.124mm]
Silk To Solder Mask Clearance Constraint: (0.124mm < 0.15mm) Between Pad LED4-1(178mm,99.5mm) on Top Layer And Track (173.936mm,101.024mm)(179.016mm,101.024mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.124mm]
Silk To Solder Mask Clearance Constraint: (0.124mm < 0.15mm) Between Pad LED4-1(178mm,99.5mm) on Top Layer And Track (173.936mm,97.976mm)(179.016mm,97.976mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.124mm]
Silk To Solder Mask Clearance Constraint: (0.124mm < 0.15mm) Between Pad LED4-2(175mm,99.5mm) on Top Layer And Track (173.936mm,101.024mm)(179.016mm,101.024mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.124mm]
Silk To Solder Mask Clearance Constraint: (0.124mm < 0.15mm) Between Pad LED4-2(175mm,99.5mm) on Top Layer And Track (173.936mm,97.976mm)(179.016mm,97.976mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.124mm]
Silk To Solder Mask Clearance Constraint: (0.124mm < 0.15mm) Between Pad LED5_1-1(251.5mm,158mm) on Top Layer And Track (247.436mm,156.476mm)(252.516mm,156.476mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.124mm]
Silk To Solder Mask Clearance Constraint: (0.124mm < 0.15mm) Between Pad LED5_1-1(251.5mm,158mm) on Top Layer And Track (247.436mm,159.524mm)(252.516mm,159.524mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.124mm]
Silk To Solder Mask Clearance Constraint: (0.124mm < 0.15mm) Between Pad LED5_1-2(248.5mm,158mm) on Top Layer And Track (247.436mm,156.476mm)(252.516mm,156.476mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.124mm]
Silk To Solder Mask Clearance Constraint: (0.124mm < 0.15mm) Between Pad LED5_1-2(248.5mm,158mm) on Top Layer And Track (247.436mm,159.524mm)(252.516mm,159.524mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.124mm]
Silk To Solder Mask Clearance Constraint: (0.124mm < 0.15mm) Between Pad LED5_2-1(252.5mm,48mm) on Top Layer And Track (248.436mm,46.476mm)(253.516mm,46.476mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.124mm]
Silk To Solder Mask Clearance Constraint: (0.124mm < 0.15mm) Between Pad LED5_2-1(252.5mm,48mm) on Top Layer And Track (248.436mm,49.524mm)(253.516mm,49.524mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.124mm]
Silk To Solder Mask Clearance Constraint: (0.124mm < 0.15mm) Between Pad LED5_2-2(249.5mm,48mm) on Top Layer And Track (248.436mm,46.476mm)(253.516mm,46.476mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.124mm]
Silk To Solder Mask Clearance Constraint: (0.124mm < 0.15mm) Between Pad LED5_2-2(249.5mm,48mm) on Top Layer And Track (248.436mm,49.524mm)(253.516mm,49.524mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.124mm]
Silk To Solder Mask Clearance Constraint: (0.124mm < 0.15mm) Between Pad LED6_1-1(251.5mm,154mm) on Top Layer And Track (247.436mm,152.476mm)(252.516mm,152.476mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.124mm]
Silk To Solder Mask Clearance Constraint: (0.124mm < 0.15mm) Between Pad LED6_1-1(251.5mm,154mm) on Top Layer And Track (247.436mm,155.524mm)(252.516mm,155.524mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.124mm]
Silk To Solder Mask Clearance Constraint: (0.124mm < 0.15mm) Between Pad LED6_1-2(248.5mm,154mm) on Top Layer And Track (247.436mm,152.476mm)(252.516mm,152.476mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.124mm]
Silk To Solder Mask Clearance Constraint: (0.124mm < 0.15mm) Between Pad LED6_1-2(248.5mm,154mm) on Top Layer And Track (247.436mm,155.524mm)(252.516mm,155.524mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.124mm]
Silk To Solder Mask Clearance Constraint: (0.124mm < 0.15mm) Between Pad LED6_2-1(252.5mm,44mm) on Top Layer And Track (248.436mm,42.476mm)(253.516mm,42.476mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.124mm]
Silk To Solder Mask Clearance Constraint: (0.124mm < 0.15mm) Between Pad LED6_2-1(252.5mm,44mm) on Top Layer And Track (248.436mm,45.524mm)(253.516mm,45.524mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.124mm]
Silk To Solder Mask Clearance Constraint: (0.124mm < 0.15mm) Between Pad LED6_2-2(249.5mm,44mm) on Top Layer And Track (248.436mm,42.476mm)(253.516mm,42.476mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.124mm]
Silk To Solder Mask Clearance Constraint: (0.124mm < 0.15mm) Between Pad LED6_2-2(249.5mm,44mm) on Top Layer And Track (248.436mm,45.524mm)(253.516mm,45.524mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.124mm]
Silk To Solder Mask Clearance Constraint: (0.124mm < 0.15mm) Between Pad LED7-1(38mm,65.5mm) on Top Layer And Track (36.476mm,64.484mm)(36.476mm,69.564mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.124mm]
Silk To Solder Mask Clearance Constraint: (0.124mm < 0.15mm) Between Pad LED7-1(38mm,65.5mm) on Top Layer And Track (39.524mm,64.484mm)(39.524mm,69.564mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.124mm]
Silk To Solder Mask Clearance Constraint: (0.124mm < 0.15mm) Between Pad LED7-2(38mm,68.5mm) on Top Layer And Track (36.476mm,64.484mm)(36.476mm,69.564mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.124mm]
Silk To Solder Mask Clearance Constraint: (0.124mm < 0.15mm) Between Pad LED7-2(38mm,68.5mm) on Top Layer And Track (39.524mm,64.484mm)(39.524mm,69.564mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.124mm]
Silk To Solder Mask Clearance Constraint: (0.149mm < 0.15mm) Between Pad U9_1-10(233.334mm,144.69mm) on Top Layer And Track (234.281mm,143.621mm)(234.281mm,148.955mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.149mm]
Silk To Solder Mask Clearance Constraint: (0.149mm < 0.15mm) Between Pad U9_1-11(233.334mm,145.325mm) on Top Layer And Track (234.281mm,143.621mm)(234.281mm,148.955mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.149mm]
Silk To Solder Mask Clearance Constraint: (0.149mm < 0.15mm) Between Pad U9_1-12(233.334mm,145.96mm) on Top Layer And Track (234.281mm,143.621mm)(234.281mm,148.955mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.149mm]
Silk To Solder Mask Clearance Constraint: (0.149mm < 0.15mm) Between Pad U9_1-13(233.334mm,146.595mm) on Top Layer And Track (234.281mm,143.621mm)(234.281mm,148.955mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.149mm]
Silk To Solder Mask Clearance Constraint: (0.149mm < 0.15mm) Between Pad U9_1-14(233.334mm,147.23mm) on Top Layer And Track (234.281mm,143.621mm)(234.281mm,148.955mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.149mm]
Silk To Solder Mask Clearance Constraint: (0.149mm < 0.15mm) Between Pad U9_1-15(233.334mm,147.865mm) on Top Layer And Track (234.281mm,143.621mm)(234.281mm,148.955mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.149mm]
Silk To Solder Mask Clearance Constraint: (0.149mm < 0.15mm) Between Pad U9_1-16(233.334mm,148.5mm) on Top Layer And Track (234.281mm,143.621mm)(234.281mm,148.955mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.149mm]
Silk To Solder Mask Clearance Constraint: (0.143mm < 0.15mm) Between Pad U9_1-8(228mm,144.055mm) on Top Layer And Track (227.042mm,143.621mm)(234.281mm,143.621mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.143mm]
Silk To Solder Mask Clearance Constraint: (0.143mm < 0.15mm) Between Pad U9_1-9(233.334mm,144.055mm) on Top Layer And Track (227.042mm,143.621mm)(234.281mm,143.621mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.143mm]
Silk To Solder Mask Clearance Constraint: (0.149mm < 0.15mm) Between Pad U9_1-9(233.334mm,144.055mm) on Top Layer And Track (234.281mm,143.621mm)(234.281mm,148.955mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.149mm]
Silk To Solder Mask Clearance Constraint: (0.149mm < 0.15mm) Between Pad U9_2-10(234.334mm,34.69mm) on Top Layer And Track (235.281mm,33.621mm)(235.281mm,38.955mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.149mm]
Silk To Solder Mask Clearance Constraint: (0.149mm < 0.15mm) Between Pad U9_2-11(234.334mm,35.325mm) on Top Layer And Track (235.281mm,33.621mm)(235.281mm,38.955mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.149mm]
Silk To Solder Mask Clearance Constraint: (0.149mm < 0.15mm) Between Pad U9_2-12(234.334mm,35.96mm) on Top Layer And Track (235.281mm,33.621mm)(235.281mm,38.955mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.149mm]
Silk To Solder Mask Clearance Constraint: (0.149mm < 0.15mm) Between Pad U9_2-13(234.334mm,36.595mm) on Top Layer And Track (235.281mm,33.621mm)(235.281mm,38.955mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.149mm]
Silk To Solder Mask Clearance Constraint: (0.149mm < 0.15mm) Between Pad U9_2-14(234.334mm,37.23mm) on Top Layer And Track (235.281mm,33.621mm)(235.281mm,38.955mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.149mm]
Silk To Solder Mask Clearance Constraint: (0.149mm < 0.15mm) Between Pad U9_2-15(234.334mm,37.865mm) on Top Layer And Track (235.281mm,33.621mm)(235.281mm,38.955mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.149mm]
Silk To Solder Mask Clearance Constraint: (0.149mm < 0.15mm) Between Pad U9_2-16(234.334mm,38.5mm) on Top Layer And Track (235.281mm,33.621mm)(235.281mm,38.955mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.149mm]
Silk To Solder Mask Clearance Constraint: (0.143mm < 0.15mm) Between Pad U9_2-8(229mm,34.055mm) on Top Layer And Track (228.042mm,33.621mm)(235.281mm,33.621mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.143mm]
Silk To Solder Mask Clearance Constraint: (0.143mm < 0.15mm) Between Pad U9_2-9(234.334mm,34.055mm) on Top Layer And Track (228.042mm,33.621mm)(235.281mm,33.621mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.143mm]
Silk To Solder Mask Clearance Constraint: (0.149mm < 0.15mm) Between Pad U9_2-9(234.334mm,34.055mm) on Top Layer And Track (235.281mm,33.621mm)(235.281mm,38.955mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.149mm]
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Net Antennae (Tolerance=0mm) (All)
Net Antennae: Via (248.3mm,108.55mm) from Top Layer to Bottom Layer
Net Antennae: Via (248.3mm,109.95mm) from Top Layer to Bottom Layer
Net Antennae: Via (249mm,107.85mm) from Top Layer to Bottom Layer
Net Antennae: Via (249mm,110.65mm) from Top Layer to Bottom Layer
Net Antennae: Via (250.4mm,107.85mm) from Top Layer to Bottom Layer
Net Antennae: Via (250.4mm,110.65mm) from Top Layer to Bottom Layer
Net Antennae: Via (251.1mm,108.55mm) from Top Layer to Bottom Layer
Net Antennae: Via (251.1mm,109.95mm) from Top Layer to Bottom Layer
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